The present application claims priority under 35 U.S.C. § 119 to Korean Application No. 2000-55208 filed on Sep. 20, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly, to a dynamic random access memory device having a capacitor-over-bit line (COB) structure capable of forming a connector for connecting a bit line or a lower electrode of a capacitor with a semiconductor substrate by a one-time mask process, while providing a misalignment margin during the connector formation process, and a manufacturing method thereof.
2. Description of the Related Art
As the integration density of semiconductor devices such as dynamic RAMs (DRAMs) continues to increase, a bit line is formed under a capacitor. In association therewith, a lower electrode connector for connecting a lower electrode of a capacitor with an active area (e.g., a source region of a transistor) of a semiconductor substrate on which a DRAM is formed, and a bit line connector for connecting a bit line and another active area are formed by a two-time mask process, respectively. In this case., the lower electrode connector and the bit line connector, respectively, include a contact plug directly contacting an active area of a semiconductor substrate, and a contact pad disposed between the contact plug and the lower electrode or the bit line.
Since the contact pad and the contact plug forms a contact surface, the overall resistance of the lower electrode connector and the bit line connector increases, which in turn degrades the operating speed of a semiconductor memory device. Furthermore, to form the lower electrode connector and the bit line connector, the step of manufacturing and removing a photo mask is repeatedly performed three or four times, thereby complicating the overall process and increasing the possibility that a semiconductor substrate will suffer damage due to the repeatedly performed mask removing step. Furthermore, as the integration density of a semiconductor memory device continues to increase, there is a limit to securing a misalignment margin when forming contact holes for the contact pad and contact plug described above.
The above problems will now be described with reference to FIGS. 1–8. A semiconductor memory device shown in FIGS. 1, 2, 3, 6 and 8 is divided into a cell area C and a peripheral circuit area P, while only the cell area C of the semiconductor memory device is shown in FIGS. 4, 5 and 7. Hereinafter, a bit line contact plug and a lower electrode contact plug denote a portion directly connected with an active area of a substrate and a gate electrode, respectively, and a bit line contact pad and lower electrode contact pad denote a portion connecting the bit line contact plug with a bit line formed on the substrate and a portion connecting the lower electrode contact plug with a lower electrode, respectively. Either the bit line contact plug (or lower electrode contact plug) or the bit line contact pad (or lower electrode contact pad), or if there are the contact pad and the contact plug, the combination thereof is defined as a bit line contact connector (or lower electrode contact connector).
In FIG. 1, an active area of a semiconductor substrate 100 is defined by isolation regions 102. The isolation regions may be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technique, and in the case of a highly integrated semiconductor memory device, a STI technique is preferably used. Next, an insulating layer, a polysilicon layer, a metal layer or a metal silicide layer, and a capping layer are formed over the entire surface of the semiconductor substrate 100 on a cell area C and a peripheral circuit area P and patterned to form the gate electrodes G1, G2, G3, G4, G5, G6, G7, and G8 and capping patterns 111. Each gate electrode G1, G2, G3, G4, G5, G6, G7, or G8 is composed of a gate electrode insulating pattern 104, a polysilicon pattern 108, and a metal pattern or a metal silicide pattern 110. Then, using each gate electrode G1, G2, G3, G4, G5, G6, G7, or G8 as a mask, ions having the opposite conductive type to the semiconductor substrate 100 are implanted into the semiconductor substrate 100 to form drain and source regions 103 and 105.
The capping layer or the capping pattern 111 may be composed of a material having high selectivity with respect to an interlevel dielectric layer 112 which will later be formed, such as for example a silicon nitride layer, an aluminum oxide layer, or a tantalum oxide layer. Subsequently, an insulating layer is formed over the entire surface of the semiconductor substrate 100 on which the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8 been formed, and etched back to form a spacer 106 along the sidewall of the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8 and capping pattern 111. The spacer 106 may be composed of a material having high selectivity with respect to the interlevel dielectric layer 112. Here, the structures comprised of the gate electrodes G1, G2, G3, G4, G5, G6, G7, or G8, the capping pattern 111, and the spacers 106 are referred to as gate electrode structures.
Meanwhile, after having formed the spacer 106, impurity ions of high concentration are implanted into the semiconductor substrate 100 to form the drain and source regions 103 and 105 having a lightly doped drain and source (LDD) structure, thereby completing first through eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8. The first through fifth transistors T1, T2, T3, T4, and T5 are formed on the cell area C, while the sixth through the eight transistors T6, T7, and T8 are formed on the peripheral circuit area P. Hereinafter, the drain and source regions having a LDD structure are referred to as drain and source regions.
In FIG. 1, the transistors T1, T2, T3, and T4, or T6 and T7 between the isolation regions 102 have channels of the same conductive type. The source region 105 of the second transistor T2 is in common with that of the first transistor T1, and the drain region 103 of the second transistor T2 is in common with that of the third transistor T3. Meanwhile, the fifth transistor T5 may have the same or opposite conductive type of channel. To have a channel of the opposite conductive type to a substrate, a well (not shown) of the opposite conductive type to the substrate is formed within the substrate to form source and drain regions of an adjacent transistor.
A planarized first interlevel dielectric layer 112 is formed over the entire surface of the semiconductor substrate 100 on the cell area C and the peripheral circuit area P on which the spacer 106 has been formed. Subsequently, the first interlevel dielectric layer 112 on the cell area C is etched to form first contact holes exposing the drain and source regions 103 and 105 of the transistors T1, T2, T3, and T4. At this point, if the capping patterns 111 and the spacers 106 are composed of materials having high selectivity to the first interlevel dielectric layer 112, the first contact holes are formed using a self-aligned etching by the capping patterns 111 and the spacers 106. Next, a polysilicon layer 114 formed of a conductive material is formed on the first interlevel dielectric layer 112 including the first contact holes.
Referring to FIG. 2, chemical mechanical polishing (CMP) or etchback is performed on the polysilicon layer 114 until the top surface of the first interlevel dielectric layer 112 is substantially exposed to form a bit line contact plug 114b and lower electrode bit line contact plugs 114a and 114c connected to the drain region 103 and the source region on the cell area C of the semiconductor substrate 100, respectively. Next, a planarized second interlevel dielectric layer 116 is formed over the entire surface of the semiconductor substrate 100 including the peripheral circuit area P and bit line contact plug 114b and the lower electrode bit line contact plugs 114a and 114c on the cell area C. Then, the second interlevel dielectric layer 116 overlying the bit line contact plug 114b is etched to form a second contact hole. At the same time that the second contact hole is formed, the second interlevel dielectric layer 116 and the first interlevel dielectric layer 112 formed at the different positions are etched to form a third contact hole exposing an active area of the transistor T5 disposed on the cell area C, such as the drain region 103. Meanwhile, a process of forming a fourth contact hole exposing the metal or metal silicide pattern 110 of the gate electrode G6 on the peripheral circuit area P includes a step of etching the second interlevel dielectric layer 116 to expose the capping pattern 111 of the sixth transistor T6, which is similar to an initial step in the process of forming the third contact hole, and a subsequent step of removing the capping pattern 111 to expose the metal layer or the metal silicide pattern 110. After having formed the second through the fourth contact holes in this way, a polysilicon layer 118, which is a conductive material, is formed on the second interlevel dielectric layer 116 to thereby fill the second through the fourth contact holes.
In FIG. 3, CMP or etchback is performed on the polysilicon layer 118 until the top surface of the second interlevel dielectric layer 116 is exposed to form a bit line contact pad 118a and bit line contact plugs 118b and 118c. The bit line contact plugs 118b and 118c may be also called bit line contact pads, but in this specification bit line contact plug is used. A bit line connector for connecting the active area 103 between the transistors T2 and T3 and a bit line 120 is comprised of the bit line contact plug 114b and the bit line contact pad 118a. A bit line connector connecting the transistor T5 and the bit line 120 is the bit line contact plug 118b, while a bit line connector connecting the transistor T6 to the bit line 120 is the bit line contact plug 118c. 
Next, a metal anti-diffusion layer and a metal layer are provided over the semiconductor substrate 100 including the bit line contact pad 118a and the bit line contact plugs 118b and 118c and patterned to form a bit line 120. Titanium nitride (TiN) or titanium tungsten (TiW) is used as the metal anti-diffusion layer, while Ti, W or Al is used as the metal layer.
To protect the bit line from a subsequent integration process, an insulating layer is formed over the entire surface of the semiconductor substrate including the bit line 120 and is subjected to etchback to form a capping pattern 122 including a spacer. The insulating layer formed on the cell area C and the peripheral circuit area P is removed except for a portion in which the bit line 120 is formed, thereby shielding only the bit line 120 on the peripheral circuit area P.
Subsequently, a planarized third interlevel dielectric layer 124 is formed over the entire surface of the semiconductor substrate 100 on which the capping pattern 122 has been formed. Using a contact-type photoresist mask pattern (160 of FIG. 5), the third interlevel dielectric layer 124 and the underlying second interlevel dielectric layer 116 are etched to form a fifth contact hole 125 exposing the lower electrode contact plugs 114a and 114c of a capacitor.
Meanwhile, a plan view in which the contact-type photoresist mask pattern (160 of FIG. 5) used in forming the fifth contact hole 125 is disposed is shown in FIG. 4. Only a portion denoted by reference numeral 150 in FIG. 4 is exposed by the contacttype photoresist mask pattern (160 of FIG. 5), which corresponds to the underlying third interlevel dielectric layer 124.
More specifically, in FIG. 4, the first through fourth gate electrodes G1, G2, G3 and G4 extending in the Y-axis direction are disposed in parallel with respect to each other along the X-axis direction, and the bit lines 120 are disposed interposing the second interlevel dielectric layer 116 on the first through fourth gate electrodes G1, G2, G3, and G4 so that both meet at right angles. The lower electrode contact plugs 114a and 114c are positioned between the gate electrodes G1 and G2, and between the gate electrodes G3 and G4, respectively. The bit line contact plug 114b is positioned between the second and third gate electrodes G2 and G3 in a direction in which the gate electrodes G2 and G3 extend. The bit line capping pattern 122 and the overlying third dielectric layer 124 are not shown in FIG. 4.
In a cross-sectional view (not shown) taken along line VI—VI of FIG. 4, if an etching process for forming the fifth contact hole 125 is performed, the second and third interlevel dielectric layer 116 and 124 between the second and third gate electrodes G2 and G3 are not etched, while the second and third interlevel dielectric layer 116 and 124 between the first and second gate electrodes G1 and G2, and between the third and fourth gate electrodes G3 and G4 are removed to form the fifth contact holes 125 as shown in FIG. 3.
On the other hand, referring to FIG. 5, which is a cross sectional view taken along line V—V of FIG. 4, the lower electrode contact plug 114a self-aligned between the first and second gate electrodes extends along the gate electrodes on the semiconductor substrate 100. The second interlevel dielectric layer 116 is formed perpendicularly to the gate electrode on the lower electrode contact plug 114a. The bit lines 120 covered with the capping pattern 122 are formed on top of the second interlevel dielectric layer 116, each of which is separated in the Y direction in which the gate electrode extends. Next, the third interlevel dielectric layer 124 is disposed on the second interlevel dielectric layer 116 including the capping pattern 122, on top of which the contact-type self-aligned photoresist mask pattern 160 is positioned for forming the fifth contact hole 125 by etching the second and third interlevel dielectric layers 116 and 124 between the capping patterns 122.
Subsequently, as shown in FIG. 7, using the mask pattern 160 as an etch mask, the third and second interlevel dielectric layers 124 and 116 are etched to form the fifth contact hole 125, and then the contact-type self-aligned photoresist mask pattern 160 is removed. Next, the polysilicon layer 126 is formed over the entire surface of the semiconductor substrate 100 and subjected to etchback or CMP until the top surface of the third dielectric layer 124 is exposed.
Specifically, FIG. 6 shows a cross sectional view of a semiconductor memory device including the cell area C on which etchback or CMP has been performed on the polysilicon layer 126, taken along line VI—VI of the X-axis direction of FIG. 4, while FIG. 7 shows a cross-sectional view of the cell area C taken along line V—V of the Y-axis direction. That is, in FIGS. 6 and 7, the polysilicon layer 126 undergoes CMP to form capacitor lower electrode contact pads 126a and 126b. 
Subsequently, as shown in FIG. 6, an etching stop layer 128 provided with an opening is formed on the third interlevel dielectric layer 124 on the cell area C on which the lower electrode contact pads 126a and 126b have been formed, on top of which a lower electrode 130, a dielectric layer 132, and an upper electrode 134 constituting a capacitor are formed.
In FIG. 8, a planarized fourth interlevel dielectric layer 136 is formed over the entire surface of the semiconductor substrate 100 on the cell area C on which the capacitor has been formed, and on the peripheral circuit area P. A predetermined portion of the fourth interlevel dielectric layer 136 is etched to form a sixth contact hole exposing a portion of the upper electrode 134 on the cell area C. After having formed the sixth contact hole, predetermined portions of the third interlevel dielectric layer 124, the capping patterns 122 and 111, and the first and second interlevel dielectric layers 112 and 116 are etched to form seventh, eighth, and ninth contact holes. Here, the seventh, eighth, and ninth contact holes expose the bit line 120 on the peripheral circuit area P, the active area 103 of the semiconductor substrate 100 on the peripheral circuit area P, and the metal or metal silicide pattern 110 of the gate electrode G8, respectively. A metal layer (not shown) is formed on the fourth interlevel dielectric layer 136 in which the sixth through ninth contact holes have been formed in such a way as to fill the sixth through ninth contact hole, and then CMP or etchback is performed on the metal layer to form metal wiring contact plugs 138a, 138b, 138c, and 138d. In a subsequent process, a metal layer (not shown) is formed on the fourth interlevel dielectric layer 136 and patterned to form metal wiring contact pads 140a, 140b, 140c, and 140d. 
While the bit line contact plugs and the lower electrode contact plugs are simultaneously formed using one mask, a three-time mask process is required in order to connect the bit line 120 and the lower electrode 130 to the active areas 103 and 105 of the semiconductor substrate 100. That is, to form the bit line connector, a first mask for the bit line contact plug 114b formed simultaneously with the lower electrode contact plugs 114a and 114c, and a second mask for forming the bit line contact pad 118a are required. To form the lower electrode connector, a first mask and a third mask for forming the lower electrode contact pads 126a and 126b are required. Thus, a process for forming the bit line connector and the lower electrode connector is complicated.
Meanwhile, the bit line 120 is connected to the area 103 of the semiconductor substrate 100 through the bit line contact plug 114b and the bit line contact pad 118a, while the lower electrode 130 is connected to the active area 105 of the semiconductor substrate 100 through the lower electrode contact plugs 114a and 114c and the lower electrode contact pads 126a and 126b. Thus, the bit line connector and the lower electrode connector have contact surfaces within them, which increases the overall resistance due to occurrences of contact resistance. The increased resistance, in turn, degrades the operating speed of transistors and capacitors.
Furthermore, since the fifth contact holes 125 for forming the lower electrode contact plug 126a and 126b are separated by 1 feature size (F) and 3 F in the Y-and X-axis directions, respectively, an alignment margin for the photoresist mask pattern 160 is not sufficient. That is, if the photoresist mask pattern 160 is misaligned in the Y-axis direction, the adjacent bit lines 120 are connected to each other to cause a bridge. Furthermore, if the third interlevel dielectric layer 124 for the fifth contact hole 125 is overetched, the capping pattern 122 is removed to expose the bit line 120. As a result, an electrical short occurs between the bit line 120 and the lower electrode 130.
Thus, to provide for a misalignment margin, the thickness of the capping pattern 122, which is a hard mask formed on the bit line 120, needs to increase. However, an increase in the thickness of capping pattern 122 makes it difficult to fill the space between the bit line structures 120 and 122 with a material of the third interlevel dielectric layer 124 where the fifth contact hole 125 will be formed without a void forming.
To fill the space between the bit line structures 120 and 122 without forming a void, liquid spin-on glass (SOG) and borophosphosilicate glass (BPSG) may be used. However, oxygen contained in the SOG or BPSG penetrates under the bit line 120 to oxidize the bit line 120, thereby causing the problem of lifting the bit line 120.
Furthermore, if the mask pattern 160 is misaligned in the X- and/or Y-axis directions, an overlay margin with the gate electrodes G1, G2, G3, and G4 and the hard mask 122 formed on the bit line 120 becomes smaller, thereby offering low selectivity during a self-aligned contact (SAC) etching process.
Meanwhile, when forming the fifth contact hole 125 using the contact-type self-aligned mask pattern 160, since the mask pattern 160 does not have high selectivity with respect to the third interlevel dielectric layer 124, a portion of the underlying third interlevel dielectric layer 124 is removed, and a bridge defect occurs between the adjacent bit lines 120.
To form the metal wiring contact plugs 138b, 138c, and 138d on the peripheral circuit area P, thick third and fourth interlevel dielectric layers 124 and 136, and the first and second interlevel dielectric layers 112 and 116 must be etched. This imposes a burden on an etching process for forming the fifth contact hole 125.